Semiconductor memory devices employ an array of memory cells arranged in columns and rows to cover an area of an integrated circuit (IC) chip. The cells are addressed by means of decoder circuitry that selects the particular cell in the array that is to be either written or read out. In the read-out operation, the electrical state of the cell is read-out by means of a sense amplifier which is connected to a plurality of cells. Such a connection involves a substantial shunt or stray capacitance. When an array is made very large, the stray capacitance of the circuits is large. When a voltage responsive sense amplifier is employed, a large array entails the charging and discharging of a large capacitance. Such an action slows the speed of response. However, if the sense amplifier is made current responsive, the voltage swings can be reduced to a small value so that speed is not adversely affected by the capacitance. In particular, it is desirable to employ a current sense amplifier that reduces the signal voltage swings and yet produces a high speed high output signal.
My U.S. Pat. No. 4,464,591, issued Aug. 7, 1984, to the assignee of the present invention, discloses and claims a current difference sense amplifier. N-channel devices are disclosed in the preferred embodiment. The teaching in this patent is incorporated herein by reference.
U.S. Pat. No. 4,464,591 discloses a prior art current sense amplifier and describes its operation in detail. To summarize, the prior art circuit will respond to a 50-microampere input signal. The circuit is arranged so that this signal results in an input voltage swing of only about 20-millivolts. Such a slight voltage swing will not produce substantial charging and discharging of the memory cell capacitance. Therefore, the large shunt capacitance of a large array is not associated with a large reduction of the speed of response. However, it is shown that in the prior art circuit the size of the transistor in the signal output section must be compromised between the output signal voltage and the speed of response. Accordingly, it would be desirable to eliminate the prior art output transistor. It would also be desirable to employ complementary metal oxide semiconductor (CMOS) elements to fabricate the circuits.